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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 06/03/08 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. is61wv10248all is61wv10248bll is64wv10248bll 1m x 8 high-speed cmos static ram june 2008 features ? high-speed access times: 8, 10, 20 ns ? high-performance, low-power cmos process ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single power supply ? v dd 1.65v to 2.2v (is61wv10248all) speed = 20ns for vcc = 1.65v to 2.2v ? v dd 2.4v to 3.6v (is61/64wv10248bll) speed = 10ns for vcc = 2.4v to 3.6v speed = 8ns for vcc = 3.3v + 5% ? packages available: ? 48-ball minibga (9mm x 11mm ) ? 44-pin tsop (type ii) ? industrial and automotive temperature support ? lead-free available description the issi is61wv10248all/bll and is64wv10248bll are very high-speed, low power, 1m-word by 8-bit cmos static ram. the is61wv10248all/bll and is64wv10248bll are fabricated using issi 's high- performance cmos technology. this highly reliable process coupled with innovative circuit design tech- niques, yields higher performance and low power con- sumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. the is61wv10248all/bll and is64wv10248bll operate from a single power supply and all inputs are ttl-compatible. the is61wv10248all/bll and is64wv10248bll are available in 48 ball mini bga and 44-pin tsop (type ii) packages. functional block diagram a0-a19 ce oe we 1m x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll pin descriptions a0-a19 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 data input / output v dd power gnd ground nc no connection 48-pin mini bga (m ) (9mm x 11mm) 44-pin tsop (type ii ) 1 2 3 4 5 6 a b c d e f g h nc nc nc gnd v dd nc nc a18 oe nc nc nc nc nc nc a8 a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 ce i/o1 i/o3 i/o4 i/o5 we a11 nc i/o0 i/o2 v dd gnd i/o6 i/o7 a19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a0 a1 a2 a3 a4 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc nc nc nc a18 a17 a16 a15 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a14 a13 a12 a11 a10 a19 nc nc 44 43 42 41 pin configuration
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v v dd v dd relates to gnd ?0.3 to 4.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc read h l l d out i cc write l l x d in i cc capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll operating range (v dd ) (is61wv10248bll) (1) range ambient temperature v dd (8 n s )v dd (10 n s ) commercial 0c to +70c 3.3v + 5% 2.4v-3.6v industrial ?40c to +85c 3.3v + 5% 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. operating range (v dd ) (is64wv10248bll) range ambient temperature v dd (10 n s ) automotive ?40c to +125c 2.4v-3.6v operating range (v dd ) (is61wv10248all) range ambient temperature v dd (20 n s ) commercial 0c to +70c 1. 65v-2.2v industrial ?40c to +85c 1. 65v-2.2v automotive ?40c to +125c 1. 65v-2.2v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll dc electrical characteristics (over operating range) v dd = 2.4v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 1.8 ? v v ol output low voltage v dd = min., i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width 10 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 5% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width 10 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 1.65v-2.2v symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width 10 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width 10 ns). not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll ac test loads figure 1. 319 5 pf including jig and scope 353 output 3.3v figure 2. z o = 50 1.5v 50 output 30 pf including jig and scope ac test conditions (high speed) parameter unit unit unit (2.4v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v dd -0.3v 0.4v to v dd -0.3v 0.4v to v dd -0.2v input rise and fall times 1.5ns 1.5ns 1.5ns input and output timing v dd /2 v dd /2 + 0.05 v dd /2 and reference level (v ref ) output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll power supply characteristics (1) (over operating range) -8 -10 -20 symbol parameter test conditions min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. ? 110 ? 95 ? 90 ma supply current i out = 0 ma, f = f max ind. ? 120 ? 100 ? 100 auto. ? ? ? 140 ? 140 typ. (2) 60 i cc 1 operating v dd = max., com. ? 30 ? 30 ? 30 ma supply current i out = 0 ma, f = 0 ind. ? 35 ? 35 ? 35 auto. ? ? ? 60 ? 70 i sb 1 ttl standby current v dd = max., com. ? 30 ? 30 ? 30 ma (ttl inputs) v in = v ih or v il ind. ? 35 ? 35 ? 35 ce v ih , f = 0 auto. ? ? ? 70 ? 70 i sb 2 cmos standby v dd = max., com. ? 20 ? 20 ? 15 ma current (cmos inputs) ce v dd ? 0.2v, ind. ? 25 ? 25 ? 20 v in v dd ? 0.2v, or auto. ? ? ? 70 ? 70 v in 0.2v , f = 0 typ. (2) 4 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll read cycle switching characteristics (1) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t rc read cycle time 8 ? 10 ? ns t aa address access time ? 8 ? 10 ns t oha output hold time 2 ? 2 ? ns t ace ce access time ? 8 ? 10 ns t doe oe access time ? 5.5 ? 6.5 ns t hzoe (2) oe to high-z output ? 3 ? 4 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzce (2 ce to high-z output 0 3 0 4 ns t lzce (2) ce to low-z output 3 ? 3 ? ns t pu power up time 0 ? 0 ? ns t pd power down time ? 8 ? 10 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll read cycle switching characteristics (1) (over operating range) -20 ns symbol parameter min. max. unit t rc read cycle time 20 ? ns t aa address access time ? 20 ns t oha output hold time 2.5 ? ns t ace ce access time ? 20 ns t doe oe access time ? 8 ns t hzoe (2) oe to high-z output 0 8 ns t lzoe (2) oe to low-z output 0 ? ns t hzce (2 ce to high-z output 0 8 ns t lzce (2) ce to low-z output 3 ? ns t pu power up time 0 ? ns t pd power down time ? 20 ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4 v to v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) ( ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll write cycle switching characteristics (1,3) (over operating range) -8 -10 symbol parameter min. max. min. max. unit t wc write cycle time 8 ? 10 ? ns t sce ce to write end 6.5 ? 8 ? ns t aw address setup time 6.5 ? 8 ? ns to write end t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe 1 we pulse width ( oe = high) 6.5 ? 8 ? ns t pwe 2 we pulse width ( oe = low) 8.0 ? 10 ? ns t sd data setup to write end 5 ? 6 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 3.5 ? 5 ns t lzwe (2) we high to low-z output 2 ? 2 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. shaded area product in development
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll write cycle switching characteristics (1,2) (over operating range) -20 ns symbol parameter min. max. unit t wc write cycle time 20 ? ns t sce ce to write end 12 ? ns t aw address setup time 12 ? ns to write end t ha address hold from write end 0 ? ns t sa address setup time 0 ? ns t pwe 1 we pulse width ( oe = high) 12 ? ns t pwe 2 we pulse width ( oe = low) 17 ? ns t sd data setup to write end 9 ? ns t hd data hold from write end 0 ? ns t hzwe (3) we low to high-z output ? 9 ns t lzwe (3) we high to low-z output 3 ? ns notes: 1. test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll ac waveforms write cycle no. 1 (1,2) ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling e dge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v ih . ac waveforms write cycle no. 2 (1,2) ( we controlled: oe is high during write cycle)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll ac waveforms write cycle no. 3 ( we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll data retention waveform ( ce controlled) v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd 1.65v 1.4v data retention mode data retention switching characteristics symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, ce v dd ? 0.2v ind. ? 25 ma auto. ? 70 typ. (1) 4 t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns note: 1. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 rev. b 06/03/08 is61wv10248all is61wv10248bll is64wv10248bll ordering information industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 (8 1 ) is61wv10248bll-10mi 48 m ini bga (9mm x 11mm) is61wv10248bll-10mli 48 mini bga (9mm x 11mm), lead-free is61wv10248bll-10ti tsop (type ii) is61wv10248bll-10tli tsop (type ii), lead-free note: 1. speed = 8ns for v dd = 3.3v + 5%. speed = 10ns for v dd = 2.4v to 3.3v. industrial range: -40c to +85c voltage range: 1.65v to 2.2v speed (ns) order part no. package 20 IS61WV10248ALL-20MI 48 m ini bga (9mm x 11mm) is61wv10248all-20ti tsop (type ii) automotive range: -40c to +125c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 is64wv10248bll-10ma3 48 m ini bga (9mm x 11mm) is64wv10248bll-10ta3 tsop (type ii) is64wv10248bll-10ctla3 tsop (type ii), lead-free, copper leadframe
packaging information integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: m (48-pin) notes: 1. controlling dimensions are in millimeters. seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 mbga - 7.2mm x 8.7mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0 .24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 8.60 8.70 8.80 0.339 0.343 0.346 d1 5.25bsc 0.207bsc e 7.10 7.20 7.30 0.280 0.283 0.287 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 9mm x 11mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 ? ? 0.047 a1 0.24 ? 0.30 0.009 ? 0.012 a2 0.60 ? ? 0.024 ? ? d 10.90 11.00 11.10 0.429 0.433 0.437 d1 5.25bsc 0.207bsc e 8.90 9.00 9.10 0.350 0.354 0.358 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a ? ? 1.20 .? ? 0.047 a1 0.25 ? 0.40 0.010 ? 0.016 a2 0.60 ? ? 0.024 ? ? d 7.90 8.00 8.10 0.311 0.314 0.319 d1 5.60bsc 0.220bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 4.00bsc 0.157bsc e 0.80bsc 0.031bsc b 0.40 0.45 0.50 0.016 0.018 0.020 mini ball grid array package code: m (48-pin)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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